CLISTINE, led by Synergie Cad and supported by the Secured Communicating Solutions division, is to design a new generation of supercomputer, several innovative technologies, allowing to significantly increase performance calculations, volume capabilities treatment while reducing the energy bill and the area occupied.

The consortium activities in studying the feasibility of building a low-cost, low-power “supercomputer”, reusing ideas from SoC design, but this time rather at PCB level (“network on-board”, or “Networks-in-Package”). Same as in Multi-processor systems-on-chip (MP-SoC) and massively parallel processor arrays (MPPA), we consider for computing resources out-of-the-shelf processor elements organized as an array. But the board level provides potentially much more flexibility than single dye chip in respect. The same is even more true of interconnects, which may even be composed and assembled (using for instance optical fibers) in a custom fashion to define product families. The network itself should be time predictable and highly parallel, far more than PCI-e and even somehow better than Ethernet,  for instance, which are the solutions provided at the other end of the spectrum, for many-rack data centers and supercomputers.

Contact : Chairman of the Steering Committee
Jean-Philippe Ginestet




Next-generation Supercomputer