Inria participates to the FUI project Clistine through its teams Aoste and Nachos, from its Sophia Méditerrané Centre.
The Aoste team shares the consortium activities in studying the feasibility of building a low-cost, low-power “supercomputer”, reusing ideas from SoC design, but this time rather at PCB level (“network on-board”, or “Networks-in-Package”). Same as in Multi-processor systems-on-chip (MP-SoC) and massively parallel processor arrays (MPPA), we consider for computing resources out-of-the-shelf processor elements organized as an array. But the board level provides potentially much more flexibility than single dye chip in respect. The same is even more true of interconnects, which may even be composed and assembled (using for instance optical fibers) in a custom fashion to define product families. The network itself should be time predictable and highly parallel, far more than PCI-e and even somehow better than Ethernet,  for instance, which are the solutions provided at the other end of the spectrum, for many-rack data centers and supercomputers. We started a thorough classification of parallel program types (known as “Dwarfs” in the literature), to act as quality benchmarks to
evaluate the platform design options.
The Nachos team acts as a prototype end-user of the Clistine supercomputer architecture, with deidacted aplication using extensive parallel features in sceintific computing, and more specifically with Galerkin methods on electromagnetic and elastodynamic wave propagation problems. The key aspects is that these codes have been written using straightforward MPI libary functions for parallelization, and run of multiple general-purpose as well as specific parallel and distributed architectures. Porting those applications onto Clistine, once available, should thus be reasonalbly easy, while providing comparative benchmark information with respect to other implementations.

Next-generation Supercomputer